Lecture Recording
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Original lecture video: Google Drive
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Lark Minutes w/ Transcription: https://rong.feishu.cn/minutes/obcntyb21e78b3fmoitko18t
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Text Transcription
2021年10月13日 下午 8:37|1小时5分钟16秒
关键词: instruction、program execution mode、instruction execution model、decode rename poets、design considerations、function return instruction、story Bits instructions、instruction comma character、NR type instruction、data type support、memory access instructions、mips instruction、memory address mode、control flow instructions、music address instruction、Accessair encoding eyes、isa design aspects、performance IC design
文字记录:
Jishen Zhao 00:02
Alright so. Last time we talk about performance and today and a little bit about. I say so. Today will continue to talk about isa and hopefully finish up. I say design in today’s class. We have enough time. Right.
Jishen Zhao 00:32
So a little bit review about performance. Because performance kind of the basic and is going to be used with through this quarter for calculation and so this is all about, we have one about performance. First of our performance metrics and on top of those metrics, you should be able to calculate the average. And also apply them to calculate the CPU performance using CPI IPC. We also talk a little bit about alternative forms metrics Maps flops, so for mix you should give to calculate. It’s not offer very different from my PC. Ann for flaps at it toward the end of this quarter, when we talk about GPU will do more calculation on flops into flops so and so forth so I will leave it to be later.
Jishen Zhao 01:24
And performance laws will talk about under SLA and buy those law an an you should be able to calculate if I give you a detailed scenario, you should be able to calculate count performance. Based on those performance wise and benchmarks.
Jishen Zhao 01:41
We just say something very brief introduction about what kind of benchmarks. We typically use micro benchmarks real workload benchmarks. Each field benchmarks with people typically used to measure the performance of different types of machines.
Jishen Zhao 02:04
So on the slide. This is the basic question. But like I always said I don’t want to remember the question, but instead understand what on the slides. Is about and you can still use the performance metrics speed up to calculate and compare performance but now under the guidance of London slot.
Jishen Zhao 02:29
And I think this picture is from where to you. We talked about last time so I’m not getting too much over it. So you can apply the same kind of basic idea and even daily life.
Jishen Zhao 02:43
Cases not just performance for computers. For I say last time we introduced basics about isa first of all. What is I say and then we talk about execution model instruction execution model and? Silver I say design goals so first of all. What is I say again you can everyone has their own. Kind of for understanding, but my understanding. Hopefully it’s helpful for you as well as a contract between the software and hardware. So software use I say to determine what can capability hardware can do an hardware. You size say as a contract to tell the software, or determine. What software requirements and to help with the whole design to cannot decide what kind of power capability will be needed?
Jishen Zhao 03:40
And the way I think about. I say what exactly looks like and detail. You can think of it as a document with teacher instructions. The software part at definition part is that with this. Particular instruction desk like ask? What is the functionality of it, but the syntax in the software and how apart is what is the? Technical details of implementing the instruction.
Jishen Zhao 04:11
Anna machines for example. What is set up a plan part of the machine code without code so force? Ann. This is kind of important you want to make sure you can distinguish between what is defining I say what is not? This is also Speaking of how much you understand what is isa their basic idea OK so listen up here. I think we’ve gone through away went through those in the last lecture so not. That that get too much over it now, you can review your last lecture slides if you want.
Jishen Zhao 04:55
Add about execution mode, so we talk about program execution model versus instruction. Execution mode, so you should be able to distinguish the 2 very clearly? What is program execution mode means? If you have a program written in high level language? How does it get executed on the machine finally so you have multiple level translation or compilation an for us computer architecture?
Jishen Zhao 05:24
Class this class, we care more about instruction execution models in this dataframe from program execution model instruction execution. Model cares more about if we got one instruction or an instruction series.
Jishen Zhao 05:38
How does the machine execute instruction by instruction basically? What is step by step, the machine goes to run that instruction so there are few steps. In particular this example is about one goal for MIPS machine. The steps different types of permission architecture. We have different instruction execution model. So here in this class will take. Use this as the example. Most of time, so the steps of executing instruction, including fetch decode rename poets execute light output and next instruction.
Jishen Zhao 06:24
Alright and today will continue to discuss I say, and mostly will. Go over each stage and talk about in stage what the stage concerned with what aspect of I say design when we design. I say in this stage with.
Jishen Zhao 06:45
Particular angle Kurt now we need to consider and will talk about a few things about what how to make a good performance. I say the particular consideration when it is an essay to make it. Perform well.
Jishen Zhao 07:04
Before we get into the aspects of I say something leftover last time we didn’t get it chance to talk, too much in detail as more information about comparison between risk and 6 so. Before we start to talk about aspects of Isaiah. To give you more information on that. And so we didn’t get a chance to give you more of example risk and assist adoptions. So if you think about machines use these day or in history. A lot of the machines, you guys use maybe X86 if you have a laptop. Like my laptop or you have a desktop servers alot of the most of them, actually use X86 architecture and this is. Moreover, 6, I say.
Jishen Zhao 07:56
An other exercise say adoption can think of for older machines have VX which we address extension. Those whom you may not see too much over. Ann for risk and there are also a lot of architectures about that. For example, mix is the architecture very simple. One will be using as examples.
Jishen Zhao 08:20
Most of time and this quarter, when we talk about CPU processor architecture and core architecture, pipelining, but a lot of the embedded system today or even not invest in general. Um during servers people start to use arm processors, we heard about on this is also a risk. I say I’m happy about the uptick in arm and if you heard about Azure architecture, like. How far Natchez everyone after about it and also power PC to IBN architecture they use risk and as well?
Jishen Zhao 08:58
There are some details in each category. You can think of, but things can change. This is kind of very general very traditional adoption of Dissay. But these days have things may be a little bit different than modern design or future design may be a little bit different than what this says here for example, arm also has 64 bit instead of. Only 32 Bits and so forth so just. Keeping an eye on those this, this just very basic a traditional design considerations monitor there may be different than what I listed here.
Jishen Zhao 09:42
Some more things I want to introduce here is the win design risk versus SIS? What makes it different? Is Viscous simple single cycle instructions will assist this complex. For each instruction, but you may hate less instruction in your program so when you design. I say or or architecture, using risk versus SIS. I say. Keep in mind that the difference? Why did make a difference to make it risk or make it sick so I missed it feel things here for example forests again, you want to design instruction. To be single cycles, there’s nothing simple instructions while successor, many motorcycle operations. Um Ann for memory operations risk is slow store architecture was 6. You may use register memory or memory to memory so there’s more complex. Operations supported insists. There are more difference, so you can go over this list when you consider the difference in terms of design considerations versus risk. It’s it’s.
Jishen Zhao 11:03
Hey, you may think of there’s a trade off during the last lecture. We also talk about there’s a debate, which ones better, but the conclusions. No also served clear winner so actually in today’s.
Jishen Zhao 11:16
X86. Actually combines the benefit of both so if you run a renters exited 6 machine. I love all I say adult Sisk as I say so. We compile you still see the 6 styled assembly code, but underneath when you really need to round those instructions. Shame they have another level translation translate into what they called Micro operations. This is translation to the micro operations or definitions are micro operations may not. And the document that you can access but this is what actually the machine is running kind of cold and Michael operations or more risk like so for Intel X86 that is more very have A6 high level. I say, but have a risk inside. In that case when you run actually run those instructions you can still. Have the benefit of for sample a single cycle instructions.
Jishen Zhao 12:30
So I have an example here if you have for since like operations like a push. When you translate Michael Operations, you actually need to instruction store Ann and I. There are more and more it’s such examples. You are interested you can search for more particles alot of articles talking about Michael operations.
Jishen Zhao 13:02
I also. If you want to know more about my cooperation scheme. Here, a few things kind of general schemes that Michael operations adopt. Prison powder more. Examples basically translate 6 instruction that has one instruction has multiple tasks into more restyling instructions that each instruction just execute one. Single cycle in particular are very obvious answer kind of example is when you or 6 like instruction can do.
Jishen Zhao 13:45
Arithmetic operation an memory options actions in the single instruction. But for US risk like instruction. Mostly the memory operation and asthmatic or even adjusted accesses for in separate. Our instructions. We need to break down and there are more examples here for example, if you want to execute a function calls. A single assist like instruction will need to translate to Formica Operations, an if it’s returned from the function return instruction in 66. I say need to be transferred into. 3 of my professions that many OK.
Jishen Zhao 14:29
But again this is just the basic idea. Michael operations are specific to a switch chip or each generation of chip now, I change. Intel changes or keep adding. Michael operations now every other or every few years.
Jishen Zhao 14:45
Thanks so this is what we live over last time about A6 versus risk. And the rest of time will start to talk about aspects of lies it will go through the.
Jishen Zhao 14:58
Steps of for executing one instruction in the instruction execution model and take a look at in each of the step for each field step where it is, and I say, well, we concern about. So first of all. The step first step of executing instructions to fashion instruction from memory and you one when you fashion instruction. We use as use PC so I think the last time we talk a little bit about it. So instructions surge or your program is employ sequence of data or values that are being stored in your memory one by one and a well restoring memory is. Sequentially storing instructions 1234 and so on, so forth an when we want to find a particular instruction to execute or next instruction to execute what we use. His special register called program counter or PC. It’s a special gesture that stores. The current program counter PC of this instruction that being currently executed. You can think of PCS a pointer to a change action and you keep adding to the pointer pointer App App to add to to help you to find the next instruction. So, in that case to fetch instruction or to find the instruction to execute.
Jishen Zhao 16:31
Considering Arby’s the wealth instruction be store and then Ray at actually concerned with the Lens of installation instruction because if we have say story Bits instructions. Each instruction storage 32 Bits that is 4. Bytes then that means the next instruction. The address for the PC is the current starting of the current instruction address. Add by 4, so think about it because you’re kind of instructions for bites. So if my PC at PC. But at a granulator bites. We need to add 4 bytes in order to find the next. Construction the start point starting point of the next instruction.
Jishen Zhao 17:15
But if I were different Lens in my essay say I for 64 bit. I says that means that’s8 bytes. So to find the next instruction. My PC needs to add by 8 every time. Ann. Actually, in IC design there are different types of flavors so for determining or dissent.
Jishen Zhao 17:39
Designing the Lens of instructions when it’s fixed less when survival is so for Facebook’s plans. In this class, we’ll talk mostly about mids that is risk. I say they have a fixed. Ness of 32 Bits instructions so every instruction student groups, so you don’t need to.
Jishen Zhao 18:00
Had to consider its always PC AD by 4, it’s the next instruction to store in your memory instruction. But for machines like X86 they actually have arrival next instructions, so that means an instruction could be one. 23 or any number of bytes so in order to find a Max instruction to execute well, she needs to know what? How many bytes are there in this instruction comma character in executing? And every time we need to evaluate the current structure of the Lens in order to find the next instruction, so that makes the? Determining of the next instruction, little bit harder because it’s not fixed anymore.
Jishen Zhao 18:51
Uh but fixed Lens versus rival Lens. They have tradeoffs. That’s why still both measures, such existing today’s designs for fixed Lens, obviously makes the PC. Are easier the manipulation PC? Is easier because every time?
Jishen Zhao 19:09
I just add a PC by a fixed number? Um but the downside is that if some of the instructions. I don’t need to encode into so many Bits. I don’t need 32 Bits to represent one instruction then.
Jishen Zhao 19:24
A lot of wasted Bits that is not just not necessary so that made the code density. That means the code the number Bits that actually does the useful job is? Not less. Then the rebalance so Bible is exactly the reverse for code S. It is better because I can be fine instructional as exactly as? What is needed by the particular instruction with the job?
Jishen Zhao 19:52
Yes, but the complexity is when I need to fetch to find the next instruction. I need to evaluate every time. What is the Lens of current instruction so that makes the fashion stage it’ll be harder. Have to compromise, the 2 to find a way to. To kind of get the benefit of both there. They do have for mix table for design. I say that has 2 lanes or 4 lengths that is the they have the rebel Lens. But the number of Bits instructions are fixed to several categories, so for example, makes estwing an architecture, they have 2 wins. In that case when I want to fetch an instruction if it’s not this less than the other so makes my fashion stage a little bit easier than complete Bible ways, but still I can. Squeeze my code density a little bit because now if I have instructions to super simple I can choose the Lens that is shorter than 5A complex instruction. I can choose the construction lasted longer there at least multiple options that we can choose. So this is one aspect of isa design, you to consider.
Jishen Zhao 21:14
When is unconsidered needs to decide what the Lens of my instruction? I want to adopt and whether I want to adopt fixed Lens instructions. Is not flavor of riverlands or mixer for 2 fibers that have fixed but multiple choices so for Lance?
Jishen Zhao 21:36
The second aspect survives design, we need to consider is during encoding stage, so think of what encoding stage does. Oh, sorry decoding stage? What is decoding stage does is now I fashion instruction. I have her machine code ones and zeros the decoding stage that what it does is to understand what this instruction does. What is the meaning what is alka? Was a friend of instruction to figure the decode stage? How to decode an instruction at a refreshed.
Jishen Zhao 22:06
We need to understand how instruction typical encoded so II aspects of eyes designers encoding. Our strategy. So for us for this class with mostly will. I stuck with them. It’s type over. I say design. So, your what you definitely need to, I want to know is 3 types over. Instruction encoding aim it’s terrible by say. This is I believe Shorty introduce also in your undergraduate level can be architecture class. But if you forget take a look at this table. There’s our time I type in J tag. All time is all of the operators or registers R stands for a jester. And I have example here that’s at R, one R2 and R3, SOR. One R2R3R represents the jesters inside my processor. So who do you still remember for R one R2 and R3? What it does? Which one are? Which one is the destination so it’SR one plus R2 equals to R3 or R2 equals. Or one plus R3 or R2, plus or 3 coastal one.
Jishen Zhao 23:40
Ok, so for mid scout. I saw some of your answers already halfway. You already remember the call will you have learned for MIPS styled? I say the first? Our plan at the destination.
Jishen Zhao 24:01
Yes, so it’SR one equals to R2, plus R3 OK, although in the machine code. You when you. In code into machine code, the way we encode the the the the order is. The destination is in code at the 3rd place. So our DD stand for definition here so will encode are one and the position of 5 Bits that are already in this table here where R2 and R3 will be encoded as. Rs and RT. Ok, so this is kind of revealed that you should have learned in your undergraduate level class and rank hit the numbers here represent the number of Bits of machine code. Are we using each of the region?
Jishen Zhao 24:53
Genotype. The difference between Jade having our type is that Jade has I hear sorry. I type I type as I hear I stand for immediate immediate means a number so you can instead of AD. The instruction on here example here I can use at, I so how can I hear I already attached the mix. I say specification and or group site so? After I believe in the class material page. So I can take a look at the detailed those yourself, but hear me it isn’t number Ann is encoded as 6 Bits.
Jishen Zhao 25:34
Are appended to the end of the for the instruction special colour and a type? Jump jump for this type of instruction aspects. When we consider designing AJ type operations. So I’ll talk about shortly without control flow. So X86 for this class will not actually use too much of S86. But if you’re wondering how is it typically is encoded it can take a look at this table? So still the similar flavor, you have a plan and Aqua App called so you have opcodes and kind of the head of this instruction, but have a prefix to kind of decide some of meta data for this instruction. An after your up code you have a bunch of different versions to determining say extension and also at the end, we can also append immediate number. I am in a bracket also included number of Bits, we could have for each operation.
Jishen Zhao 26:52
So there’s a quick question about what do SH and fun quotes? So for a session, funk if you remember your previous class for SH. At NR type instruction. You can have a shift kind of operation shift so this left ship Alright ship. So SH means shipped so you can actually encode the shifting operations functionality in here for fact if you remember it’s actually for our code. The head there 6 Bits if your function you’re up codes. The type of functionality cannot be encoded in the in the 6 Bits. You need more Bits. You can use your funk version as offloading version 2. Encode board, a different type of alcohol OK. Alright. Danko.
Jishen Zhao 27:53
That was decode stage, I will skip read and RE imposed because well, I’m going to talk about together with output. I go to the execution stage where we care more about the data types.
Jishen Zhao 28:10
Ann. Something else so for data types for. Cell phone Howard at a different definitions. There’s it’s actually stands for for shuffle care about attributes of the data and for hardware would care mobile attribute of operation because data is just ones and zeros.
Jishen Zhao 28:31
Ann. It is not our most of processors will support both type of data integer and Floating Points that we use in our execution or automatic operations mostly and. Or enter hours mathematical logic when we design, the hardware. We actually can support different various type of Lens an when we design. I say we should also consider those. And for floating point. There also different types of outlines of Bits that we supported 32 bit 64 Bits. So when we design. I say we should also be aware of what’s underneath the hardware capability is? That could take that into consideration. There are more varied.
Jishen Zhao 29:20
Chance over my data type support and also processors so if interested can take a look at other types. I will not get into too much detail over here OK. And then when we get into the right output. We’re going to talk to talk about together with RE anchored Ridan rates well we? Concerned with is mostly accessing the data.
Jishen Zhao 29:52
So when we think about when I read input and write output. We need to think about first is where we can store data so. If you have a machine I can represent into this kind of diagram you have.
Jishen Zhao 30:09
Processor. I CPU CPU chip an you will also have memory those off chip memory dimms that you can insert in your PCB motherboard. And you may also have some IO input output and they have some storage disk drive attached to IO bus.
Jishen Zhao 30:33
The places where you can store data actually is not just a single place you have. Many places we can store data. So when you consider RE input lag input and consider how to design and I say to accommodate those places to store data. Think of the places are here, so first of all PC. You can think of PC, although it’s more use like a pointer. But it’s actually a special register so with gestures used to store data so PC is also a place where can store? Values. And Regestered F Lee R type instructions were just talk about you actually read input and I write to output on and we’re jesters. And the other place is your up chip memory, so will talk more about memory later this quarter.
Jishen Zhao 31:22
But when you design as they think of yeah, you have memory access instructions flow instructions. Instruction in RISC type or A6 type you also have the way of Encoding. Here instructions that we can access the memory not just the register so those are the main line 3 places.
Jishen Zhao 31:44
When you design instruction, you can access to get your data, although this drive also store instructions. But it is not typically directly access by your instructions by actually move controlled by software. So when we talk about waiting lines quarter talk about virtual memory. We can talk a little bit about how this drives or access to finger your software and virtual memory. Alright so those are 3 places or 2 places registers memory work for instruction. You can get data and you can write it out too.
Jishen Zhao 32:20
So first of all let’s talk about adjusters how you design. I say to accommodate with Dresser access, so for registers, but we can. Encoded ASR or you can use any kind of representation symbol to represent our adjuster. Some of the essay specification use dollar. I think in quasars. Also use a dollar to represent the Jester and here I use R. The letter and those registers. So you can if you still remember all last slides actually it’s a Patch inside my CPU chip. So inside the CPU chip is really close to my core of my CPU so it’s kind of for the closest place where you can get a data and that case. That means that accessing the projector so really fast. Much faster than access memory, so if you can encode your data or can store data images so try your best to store it in regressive in that case you can access very quickly. Compared to you need to go to off chip to memory to access it.
Jishen Zhao 33:31
But the downside also I think we talk about last lecture is the number of registers inside, which is a file or the pool. Rejectionism quite limited so you may not be able to squeeze all the data. You need to access in your region so far.
Jishen Zhao 33:44
Anne Anne Anne I say design toggle instruction, where we design, there may be different type over gestures, we support. There may be some special registers PC is one special gesture, but they’re also sound dressers to only to store 14 points, so for example, I put in here F zero it’s a14 point, Magister. So the Lens so floating point we’re just maybe longer than intruder adjusters. Those are reserved for 40 point that needs a longer Lens there integer adjusters.
Jishen Zhao 34:23
And this is again example for based instruction that use all registers as inputs and Outputs Storage. And how to encode it. If we store our data in memory and we need to access the memory for estate assists like instruction. You can do memory access and calculation computation at the same time, the same instruction.
Jishen Zhao 34:49
Our before MIPS instruction. You need to break down into one memory operation and one over’s market subway memory access instruction only does memory. Access. And to represent a memory in mid style instructions. We use racket. I believe in 6 instruction. They also use bracket so. For example, here are 3 with a bracket. That means our data is stored in memory address. Then the address is stored in register 3. So our 3 is used like a user. As a pointer to point you a memory location. But Arthur itself does not store to every store in the value that we need so we need to first access are 3 an fetch the value of their and user value as an address to index into my memory to find my. Data inside this particular memory address.
Jishen Zhao 35:54
At this, the other example. We typically used to encode memory address. We can have any number in front of bracket, so the second example, 20 bracket or 5. That means we need to access the memory location. That is stored in address to English is file a register 5 + 20. So say it for just a file is sources. Value is 10, then we need to use the address 10 + 20. That’s30 as address to index into memory to get that particular data so these are all. Are examples? How we encode the memory address for them? Accessing lip style instructions for X86, maybe a little bit different. But this kind of averaging or you can see that in X8 assists South pricing as well.
Jishen Zhao 36:55
Quest so, so the question is the 20 + 20 bytes. The 20 is +20. The value so think about was joining our 510. My example is address.
Jishen Zhao 37:07
So think about what it’s like my address by address then 20, is also bites. But if my addresses. Other units to 20 is the same with other units. And typically we use by actress in that case 20 is 20 bytes.
Jishen Zhao 37:25
Alright. So, an I have an example here so instead of have R3 we can do. Our 3 bracket this example, actually is formats. We don’t typically do that because in this example. We have calculation error. Add and memory access at the same time, the same instruction. Typically, in MIPS Instruction will have her need to break it down into 2 instructions once to load or 3 to some other adjuster and then we add by only adjusters here.
Jishen Zhao 38:03
Immediate so aside from adjusters memories we can also directly store or data insider instruction. That means we encode. Immediate number is our instruction. See if we have a example. You know, I don’t have an example. We need it.
Jishen Zhao 38:24
So if I have AA median number say 36 and to represent a meeting number in mix instruction. We need to have a mark over here to represent its immediate number. So if ever any number of directly in my instructions say at IR. One R236. That means I’m going to calculate as our 2 + 36 the value an stored value to our one. So we can embed the value of the number directly inside our instruction as well.
Jishen Zhao 38:59
Ok, we have a question is the address they mode just referring to memory operations. Yes. Will talk about adressing mode shortly more I’ll give you more examples OK? And so how many registers the quick answer is there’s limited so different architecture will have different number of limited registers can, we have for as many as possible. No, because I think of my CPU chip is stressed this week, so we can only pack this many registers into this limited area. So if you want to be the how memory looks like this what the memory.
Jishen Zhao 39:46
Looks like we’ll talk about more later this quarter about the memory, particularly was well focused on the memory with the. Was a unit of this class and logically the data storing memory. You can think of? There’s a flat address space and then each block of memory will have its address. If my what unit is byte so my address is Bitaddress Ann.
Jishen Zhao 40:14
When we encode an instruction to load store instruction memory instructions were using memory address mode. We encode the address into our instructions or store into a register that we can use to access this memory to find the particular location that we want access.
Jishen Zhao 40:33
Ok. So question there is a question about does this. Provide me memory main memory come from. This yes, so if we’re talking about referring the picture on the left hand side. Of the slide, yes, this is where in the main memory is OK or this is what we could talk about we manage memory. Main memory OK will talk about more later on during this course you will see more. Alright so addressing mode, I said, I’m going to have more details so improve is when we talk about addressing only give 2 examples, but actually there’s very various ways of addressing modes so there’s less of more.
Jishen Zhao 41:18
And I believe, and the first homework every night in home first homework. You will definitely divine his classroom. Seymour example access for you to kind of try out different addressing modes in different interactive instructions OK and will give you more detailed examples. But H address in mall, we may give it a name. Those names that are used to represent what this addressing modes.
Jishen Zhao 41:52
The key feature of it. For example, displacement is as example shows. As the address in knowledge, we use for adjuster plus a median number to help you to calculate address over particular location. We can also have think that space where we have 2 adjusters together. How to quickly address so equations are here you can read it back after class if you forget about we have learned before.
Jishen Zhao 42:26
Ok and there are more complex addressing more scale. An PC relative. Those are more complex than the other ones scaled you have something multiply to the register so you get for example. Here. Or 3 multiplied by the number so you can even do some calculation on top of her. Dresser values to get their address so this is more complex scale means you actually have a multiplication and we just. Me about you.
Jishen Zhao 42:55
And PC relative you can because PC is also special adjuster so to get address. You can even leverage. The PC with the store in your PC riches are currently so that means what you store in with your executing. The current instruction, the PC you can use that to to index into the memory so this memory location related to what the current instruction is. So there are more examples over addressing modes.
Jishen Zhao 43:26
And the difference between Maps are addressing mode and X86 other symbols. As for Maps comma like can I talk too much because where they have that in previous slides an 4X +6?
Jishen Zhao 43:40
I want to put a few words for X86. Lot of their memory access are done you can see a lot of move instruction. Those are nodding. Mips instruction in. I say typically but he accesses we use move a lot and. Um using move instructions you actually can see a lot of similar type of addressing modes that ask them lips, so for example, absolute you can also have that as a zero. Person upset you have the numbers and you can also use the register the same as Maps too. To store an address the same as snips, they will have displacement if you still remember from previous slice the first type of addressing modes and there is displacement. Back in the day, but it’s just your offset could be different double Bits. Time we can also have Pentax scaled so this is a nice lips. I will not get into too much of detail.
Jishen Zhao 44:48
Ok. So this is all about adressing modes. Ann. We’ve pretty much down was sort of aspects. The laughing over aspects before we take a break. Question about is all S86 address in most special case of scaled. You can think of that, but how to make things clear. Now we just characterize into different address in motion give the number so he know specifically.
Jishen Zhao 45:24
What kind of addressing modes you’re using Angus particular instruction? Ok, so the last aspect is how to find the next instruction. So this is also related to fetch the first stage. Best way because it’s related to the Lens of instructions because the math instruction. The stage will also material manipulating PC to determine what is next PC that we want to access? But. This is more complex than only considering the Lens of instruction because for instruction there.
Jishen Zhao 46:06
Some types of instruction dash. A does jumps so this is concerned with when we have a jump instruction, we have branched. We have control flow how to find the next instruction. So then it’s not as straightforward as PC Plus an offset we need to drop. We need to compute the target do some calculation to figure out what is next PC so there’s different type of control flow instructions as well and lips? The first is PC relative as an example. I put in here and then we have absolute this is kind of easy absolutely is just J2 somewhere. I think I have example here def with yeah that’s good so.
Jishen Zhao 46:54
L3, here you can think of it just assemble over we put it in front of particular line of code and was joining L3 is the PC of. That line of code so although in this example. I didn’t look at on line but L3 means the line of code is actually the first line of code and some of the programs compiled assembly code will look like this, but. But you should be able to know that there actually L3 represents the PC out the annual music address instruction. So if I jump to help doing that means whatever I am. Currently, I would jump to his first line of goal. And the next instruction for PC relative. We have all 3 as well, but we need to do some calculation OK. Now, especially will be using branch and jump with the function.
Jishen Zhao 47:57
There’s also other type over control flow instructions in MIPS reuses register interact for example, here J jump, but we have our here are represented gestures, so whenever we see op code. They are then all we know the next appended often is actually registered so we can do the dress or something. This is very commonly using returns.
Jishen Zhao 48:22
Which and dynamical calls. This example here. This piece of code in my previous class people try to figure out what is there? Particular functionality of it, but this just for representation don’t try to figure out with the code particular test. At least actually nonsense just for for represent for demonstration of different types of.
Jishen Zhao 48:47
Control 4 instructions. There are more different type of control flow instructions. If we have time I can give you more example or otherwise I can put into your exercise for homework. So you can see more examples. Hear more about testing conditions so A. Arm and X86 call for example, here you can actually have a test condition so if you typically cope with high level language. Like C plus plus stores test condition as well, and for example, you can also do that. How many are getting into too much detail that’s just like very common? Control flow instructions. Right so I think we’re going to take a quick break over 10 minutes and when we get back at 3:07. Quickly. Go through how to make the performance better with ice and design. If we can finish OK. So we could take a break until 3:07 and will get back and continue.
Jishen Zhao 50:22
Ok, so we talk about 5 aspects advisor design and the order of our stage 5 stage of MIPS instruction, typically but. Like there are various types of I says architectures and.
Jishen Zhao 50:42
Nowadays, I say actually more complex than what will cover in here in his class actually. I say can support various Azure functionalities in operations so it. Yes, if you have examples here for example, and how she can support for 32 bit full point values into 128 bit registers. So their address to file manipulation. Accessair encoding eyes is definitely can be more complex than what we use here but.
Jishen Zhao 51:20
Hi this class is just meant to give you very basic idea why I say design. All we need. You need to know when the later on if you need to explore more complex designs so. Well, just stop over here in terms of isa design aspects. But if we need. Feel free to read about model complex words. You can use this as a list for to study as well. I’ll give you one XA code example actually said a question or kind of exercise for you to do, if your interest is not required if you’re interested you can actually take those 3 SA. Code example you can use a poster tool here to exam.
Jishen Zhao 52:08
Sammy’s nippies. Difference between X86 and aren’t you can use different compiler. Optimization options and can see. What’s the difference between the 2 type of ISIS, and how those called example, generating 2 different assembly code OK. We can do it is self interested that again is not required.
Jishen Zhao 52:35
Alright so will quickly go through the how to redesign I say if you want to optimize performance because that way things we learn about performance. And performance is going to be our optimization code this class. So when we learn. This new component in computer wanna know how to improve performance and we design on this component as I say OK. I don’t think we’re going to go through the 2 rules. There are 2 rules. But hopefully we can go through number rule number one thing to this class will Easton will number 2 to next week. Hey so rule number one is we design.
Jishen Zhao 53:16
I say consider to make the common case fast. What does it mean I’ll give you a few examples? So the first day of May come in case fast is think about alignment or grant access granularity in that case so.
Jishen Zhao 53:35
I’ve caught or and data typical address byte by byte you can access the smaller question reality over data. Program and his fight one by here. Is when you actually store data inside your memory or encode the data you? Did think of whether they’re aligned or not in particular access point in warranty. So considering the alignment if you are make the similar when we consider the Lens so far instruction code.
Jishen Zhao 54:13
If everything had lined up for your access will be easier to kind of determine where to access the word next to access but you will reduce the density over data storage and otherwise. The trade off will be reversed so when you design eyes.
Jishen Zhao 54:29
You would need to think about what is the common case of the kind of applications or programs or software running an through determine? Whether you wanna choose to be a line or online or a mix or weather or what kind of access square right here. You want to choose anyone so design. So this is the example over I said design consideration, so you need to think about what is coming.
Jishen Zhao 55:01
Determining success language in alignment. And if there’s a case that you need to handle an alignment say. There’s a not the common case distance say you already turning the alignment. An access right in there. The case you still need to handle in alignment or you decide you’re going to choose. We don’t want to choose the alcohol everything is online. You need to handle the online case is an an practice. There are different will handle it.
Jishen Zhao 55:41
I haven’t have a few examples over here. Maps an iron an earlier. Versions like she took the route of this allow everything user behind so for example, the mix. Everything needs to be 32 bit online. Um Ann for X86 and later on versions. They allow the online map.
Jishen Zhao 56:07
But supporters in hardware, so online access is still be slower. Because this complex to handle but as significant hardware complexity as well. But. As I said if income in case there’s benefit. So there’s always the requirement to support that.
Jishen Zhao 56:30
Are there other ways you can use the software you can check to software routing to handle online cases as well? In case we don’t need to modify the hardware, but. Software typical events lower suffer routines. Typical run slower than hardware component hard coded design, so there may be some high penalty when things Sir. Your access is online.
Jishen Zhao 57:03
So a question there’s a question on. Ann. Why would an ally access lays to multiple physical memory accesses but so online case is not necessary to always lead to more physical memory accesses but an online case need to figure out.
Jishen Zhao 57:22
What is the starting point of your next success so that will definitely make things more complex? And you can use in terms of software can also use compiler to handle that.
Jishen Zhao 57:38
I wanna get into too much detail of the compiler design, maybe you will learn that more compile class an for MIPS isa design. Highline accesses can also down by compiler using the 2 instructions well in this class will not actually deal with that, too much, but for information. Interested you can use those 2 instructions LWL LWR to handle those online cases in case there is with the help of compiler. But again will not get into the detail component is I. Yes. This is another exercise left leave to you for after class if you’re interested again is not required. So I think many of you should already have answer at this structure.
Jishen Zhao 58:35
Now the question is how big company, based in this structure. Ok. If. Things are a line OK. So I’ll leave it to you to consider request. Another thing about making the performance better when you consider IC design is an Indian. Yes. So Andy and this may be already heard about it. Maybe not it’s whereas you’re starting fights were starting address is. So there’s2 flavors Maps PowerPC an arm, they use big endian. This design, so I have a definition here. We just read it out big endian is the most submitted.
Jishen Zhao 59:28
Significant byte something first bite unless overbite. Hope the data is placed at the back with the lowest address. What does it mean so I have an example here if there’s A4 byte number or by integers the vertical energy for bites. Our value is 515, you can carefully calculate yourself this is a very. Traditional or what we familiar with the world represents the number of 5. 5. Binary so we can take away this winery and it’s5 . 5. But an exit is 6 the actual way over storing this data. There’s515. That’s data in memory that’s how it should reverse. So you can see the high order Bits. We typically familiar with the way we store. It was big endian. Alex reverse is actually in the lower order Bits and bytes. Just pay attention to the way of ordering is at a granular 2 bytes not Bits so. We divide this number into a bit less bytes and bytes, therefore bites. So we just reorder the back. It’s not a bit OK. So that means the little endian as means that the lab the least significant byte.
Jishen Zhao 01:00:58
Of the data is placed at a bite with the lowest address OK. Representation and I say was big endian little endian. They have trade off so that means why they both exist. Although a different architectures when a MIPS and arm style learning access Excel? So. I leave it to concerning why the trade opportunity shoot yourself. I would just give you sort of hints so for little little little Andy and the benefit is that integer cats? What is. But do you know what is integer casts? Type conversion of integer source for example, long into short integers. Those are kind of easy to deal with little endian and for big endian sign checks or? Super so leave it to you to think about why that’s the case OK after class.
Jishen Zhao 01:02:03
Hey, I think we have one minute left, I’ll just talk about this one. This example again for considering the high performance IC design. An number rule number one for making comment response so another thing for example, when considering. Using register or memory. As the op rainbow. So again there’s a tradeoff between register memory register faster, but there’s limited open memory is a very big so typically you should be able to store everything but it’s slower. Much lower than yesterday. We have a question is the address on the left smaller than right. Which side? With the previous one.
Jishen Zhao 01:02:57
The address on the. Smaller this is starting address. So the big endian is the traditional way we store so the right is the starting address here, but little endian is diverse.
Jishen Zhao 01:03:14
Because of time, let me just finish this line. Right. So for low store architectures memory access instructions load and stores were distinct and we have also we have for so the same most architecture means. Put it in other ways.
Jishen Zhao 01:03:35
Some it’s like risk liking architecture. Science says so will separate memory accesses an calculation and for complex. Our instruction designs like X8066 like we can mix them altogether. So when you design. I say pick which flavor to use you want to think about what is the common case.
Jishen Zhao 01:04:02
Sir tradeoff between 2 if your programs. You typically run our machine favors one over another then you know which one to adopt. If most for example, your program, mostly can accommodate their input output with gesture definitions adopts the regions, mostly their adjuster calculations because you’re less likely to customer.
Jishen Zhao 01:04:29
Right so I think I’ll stop here for today because there’s already we’re out of time an. This is an example of her. X86 operating mode, you can take a look at it. This example after class and then we’ll talk about it next week. On Tuesday and will also finish up with my essay by talking about the second rule of making the performance better. Right OK hold your questions about today’s lectures on Piazza or otherwise can come to my auntie’s office hour to discuss. And I think that’s all for today. Thank you for returning see you next week.